(1) Field of the Invention
The present invention relates to a clock phase detecting circuit, and more particularly, to a clock phase detecting circuit provided in a receiving section of a multiplex radio apparatus.
(2) Description of the Related Art
Generally, a receiving section of a multiplex radio apparatus is provided with a clock regenerating circuit. The clock regenerating circuit, which is also called BIT (Bit Timing Recovery), usually regenerates a clock component from a signal which is obtained by demodulating a multilevel quadrature modulated signal modulated according to PSK (Phase Shift Keying), QAM (Quadrature Amplitude Modulation) or the like, and supplies, as a sampling clock signal, to a discriminator (A/D converter) which primarily serves to discriminate received data.
The clock signal regenerated by the clock regenerating circuit must be exactly in phase with the timing at which the level of the demodulated signal is to be discriminated, but in some cases, the phase of the regenerated clock signal becomes deviated due to variations in channel conditions attributable to temperature change etc.
It is therefore necessary that the clock signal regenerated by the clock regenerating circuit should be subjected to phase correction, but in order to carry out such correction, a clock phase detecting circuit capable of detecting a clock phase deviation with high accuracy is required.
FIG. 24 is a block diagram showing the arrangement of a receiving section of a conventional multiplex radio apparatus. In FIG. 24, a signal which has been subjected to multilevel quadrature modulation, such as PSK, QAM or the like, in a transmitting-side multiplex radio apparatus (not shown) is transmitted to the receiving-side multiplex radio apparatus which, on receiving the signal, performs frequency conversion on the received signal. The frequency-converted IF signal is input to a quadrature detecting section 101, which then outputs two baseband signals (Ich signal and Qch signal) having their phases shifted by 90.degree. from each other to respective discriminating sections 102 and 103. The discriminating sections 102 and 103 each sample the corresponding signals, which have been demodulated by the quadrature detecting section 101, in accordance with a predetermined clock signal, then discriminate the sampled signals by means of a predetermined discrimination level, and convert the signals to digital signals. An equalizer 104 performs an equalization process on each of the digital signals output from the discriminating sections 102 and 103.
Based on the Ich signals input to and output from the equalizer 104, a phase component detecting section 105 detects the phase component of a clock signal (signal discrimination clock signal) for the signal discrimination at the discriminating sections 102 and 103, and outputs the detected phase component to an integrator 106. The integrator 106 averages the phase component output from the phase component detecting section 105, and outputs the result to a phase shifter 107 as a control signal for phase adjustment. Based on the phase adjustment control signal supplied from the integrator 106, the phase shifter 107 adjusts the phase of an A/D conversion clock signal generated by a clock regenerating section 108, and supplies the thus-adjusted clock signal to the discriminating sections 102 and 103. The clock regenerating section 108 regenerates the clock signal for A/D conversion based on the IF signal which is not yet subjected to the detection by the quadrature detecting section 101.
FIG. 25 is a block diagram showing the internal arrangement of the phase component detecting section 105. In FIG. 25, a gradient determining section 110 detects the gradient of the Ich signal, that is, it determines whether the Ich signal is increasing or decreasing with time. This is performed to determine in which direction phase deviation should be corrected. An error detecting section 111 comprises a subtracter and calculates the difference between the Ich signals input to and output from the equalizer 104, to thereby detect the error between the input and output signals to and from the equalizer 104. This error corresponds to the amount of phase deviation. A clock phase computing section 112, which comprises a multiplier, multiplies the output of the gradient determining section 110 by the output of the error detecting section 111 and outputs phase deviation information (phase component) for the A/D conversion clock signal. A signal determining section 113 determines whether or not the phase deviation information (phase component) output from the clock phase computing section 112 is reliable information. Specifically, only when the Ich signal is monotonously and steeply increasing or is monotonously and steeply decreasing, it is judged that the phase deviation information (phase component) output from the clock phase computing section 112 is reliable information; otherwise it is not desirable that the phase deviation information (phase component) output from the clock phase computing section 112 be used for the adjustment of the phase of the A/D conversion clock signal generated by the clock regenerating section 108. Accordingly, the signal determining section 113 determines whether or not the signal point of the Ich signal input to the gradient determining section 110 and the error detecting section 111 falls within a specific region (a range of predetermined level difference from the normal position of the signal point) on a so-called eye pattern, and if the signal point falls within the specific region, the signal determining section 113 judges that the phase deviation information (phase component) output from the clock phase computing section 112 is unreliable information. A selecting section 114, which comprises a flip-flop, outputs the phase deviation information (phase component) for the A/D conversion clock signal only when the signal determining section 113 judges that the signal point of the Ich signal input to the gradient determining section 110 and the error detecting section 111 does not exist in the specific region on the eye pattern; otherwise it outputs the previous phase deviation information.
In cases where deep phasing is occurring in the transmission channel between the transmitting section and the receiving section of multiplex radio apparatuses, there is generally observed a decrease of the high-frequency component in the frequency spectrum of the baseband signals input to the equalizer 104 of the receiving section of the conventional multiplex radio apparatus. Therefore, the signal point shows a moderate level change, so that the shape of the eye pattern near the signal point of the Ich signal becomes relatively flat. As a result, the probability that the signal point of the Ich signal is judged to be within the specific region on the eye pattern by the signal determining section 113 of the phase component detecting section 105 increases, which in turn lessens the frequency with which the selecting section 114 outputs reliable phase deviation information (phase component).
Thus, when deep phasing is occurring, a problem arises in that the phase of the A/D conversion clock signal supplied to the discriminating sections 102 and 103 cannot be quickly corrected with stability. This problem is noticeable especially in the case where a decision feedback equalizer (DFE) is employed as the equalizer 104.